(1) Field
This invention relates to a memory control device and, more particularly, to a memory control device that controls access to a memory having a plurality of banks in a storage area.
(2) Description of the Related Art
In recent years communication networks have made great strides with the rapid spread of the Internet. In particular, data communication represented by internet protocol (IP) packet communication is becoming the mainstream of traffic on all networks. In addition, device capacity, for example, has become conspicuously large because of a rise in demand for communication services or an increase in communication speed.
A router and a switch for performing packet transfer are located on such a communication network. They are used to exercise quality of service (QoS) control for transferring a packet, while ensuring packet communication quality.
With QoS control, control is exercised for outputting packets in order that is different from the order in which they arrive on the basis of quality information each packet has. Accordingly, it is necessary to locate a packet buffer as a memory for storing packet data until the outputting of the packets.
As a result, a large capacity packet buffer and high-speed access to the packet buffer are essential to data communication in which large capacity and high speed are needed. A packet buffer must efficiently be used.
Usually a dynamic random access memory (DRAM) is used as a packet buffer. A DRAM has a plurality of blocks which are called banks and in which memory cells can operate independently (typical DRAM is a synchronous DRAM (SDRAM) which is synchronized with a clock and which generally has 4 banks). Each bank is separated by a row address and a column address.
A DRAM has a simple structure (inexpensive) and a large capacity memory chip can be mounted on one device. As a result, DRAMs are widely used as packet buffers, main memories in computers, and the like.
To control access to a DRAM, a packet is disassembled into areas called segments, a write command or a read command is generated by the segment, and packet data is written/read out.
When the same bank is accessed or write/read is switched, wait time (wait) is required. Therefore, a temporal restriction is put on access.
FIG. 16 is a view showing a time chart of a DRAM interface. It is assumed that a DRAM has 4 banks b1 through b4. The interface shown in FIG. 16 is used for serially accessing each bank.
In an interval T1, data is written once to each of the banks b1 through b4, that is to say, the cycle of write access to the banks b1 through b4 is performed. In an interval T2, data is read out once from each of the banks b1 through b4, that is to say, the cycle of read access to the banks b1 through b4 is performed.
A minimum access unit shown in FIG. 16 indicates minimum access time during which one bank is accessed and corresponds to the length of data written to a bank by one access or the length of data read out from a bank by one access. In the example shown in FIG. 16, written data d1 through d4 or read data d11 through d14 corresponds to one segment.
[C1] The data d1 is written to the bank b1 by a write command w1.
[S1a] The writing of the data d1 to the bank b1 is begun in the cycle C1. After that, write access to the bank b1 cannot be gained from cycles C2 through C4. That is to say, a bank constraint is imposed (that is to say, time during which the bank b1 cannot be accessed exists). The bank b1 can be accessed next in or after a cycle C5.
[C3] The data d2 is written to the bank b2 by a write command w2.
[S2a] The writing of the data d2 to the bank b2 is begun in the cycle C3. After that, write access to the bank b2 cannot be gained from cycles C4 through C6. That is to say, a bank constraint is imposed. The bank b2 can be accessed next in or after a cycle C7 (write access is then performed in the order of the banks b3 and b4 and the same bank constraint is imposed on each of the banks b3 and b4).
[C11] The data d11 is read out from the bank b1 by a read command r1.
[S3a] The reading of the data d11 from the bank b1 is begun in the cycle C11. After that, read access to the bank b1 cannot be gained from cycles C12 through C14. That is to say, a bank constraint is imposed. The bank b1 can be accessed next in or after a cycle C15.
[C13] The data d12 is read out from the bank b2 by a read command r2.
[S4a] The reading of the data d12 from the bank b2 is begun in the cycle C13. After that, read access to the bank b2 cannot be gained from cycles C14 through C16. That is to say, a bank constraint is imposed. The bank b2 can be accessed next in or after a cycle C17 (read access is then performed in the same way in the order of the banks b3 and b4 and a bank constraint is imposed on each of the banks b3 and b4).
[S5a] When switching from write access to read access is performed, a write/read switching constraint is imposed (when switching from write access to read access or switching from read access to write access is performed, time during which an applicable bank cannot be accessed exists).
FIG. 17 is a view showing a time chart of a DRAM interface. It is assumed that there are 4 DRAMs #1 through #4. The interface shown in FIG. 17 is used for accessing a bank of each DRAM in parallel. Write access is performed in an interval T1a and read access is performed in an interval T2a. 
[C1] Data d1, d2, d3, and d4 are written to arbitrary banks of the DRAMs #1 through #4, respectively, by a write command w1.
[S1b] When the writing of the data d1 through d4 to the DRAMs #1 through #4, respectively, is begun in the cycle C1, a bank constraint is imposed.
[C5] Data d5, d6, d7, and d8 are written to arbitrary banks of the DRAMs #1 through #4, respectively, by a write command w2. To write the data d5 through d8 to arbitrary banks, this writing is begun in a cycle C5. The bank constraint imposed because of the writing in the cycle C1 is removed before the cycle C5, so access to the same banks that are accessed in the last writing can also be gained.
[S2b] When the writing of the data d5 through d8 to the DRAMs #1 through #4, respectively, is begun in the cycle C5, a bank constraint is imposed.
[C11] Data d11, d12, d13, and d14 are read out from corresponding banks of the DRAMs #1 through #4, respectively, by a read command r1.
[S3b] When the reading out of the data d11 through d14 from the DRAMs #1 through #4, respectively, is begun in the cycle C11, a bank constraint is imposed.
[C15] Data d15, d16, d17, and d18 are read out from corresponding banks of the DRAMs #1 through #4, respectively, by a read command r2. In this case, reading is begun in a cycle C15. The bank constraint imposed because of the reading in the cycle C11 is removed before the cycle C15, so access to the same banks that are accessed in the last reading can also be gained.
[S4b] When the reading out of the data d15 through d18 from the DRAMs #1 through #4, respectively, is begun in the cycle C15, a bank constraint is imposed.
[S5b] A write/read switching constraint is imposed because switching from write access to read access is performed.
In the past, a technique for reading out data to be included in a sent packet and writing data included in a received packet in parallel has been proposed as a memory access technique (see Japanese Patent Laid-Open Publication No. 2002-344502, Paragraph Nos. [0033] and [0034] and FIG. 1).
As stated above, access to a DRAM is controlled in the following way. After one bank is accessed, wait time is required to access the bank again. Accordingly, the following method, for example, is used for disassembling a packet into segments. With a serial interface for accessing 4 banks, banks b1, b2, b3, and b4 are accessed in that order and the cycle of access to the banks b1 through b4 is then performed again in the same way. A packet is disassembled into segments on the basis of the amount of data written by the cycle of write accesses to the banks b1 through b4 or the amount of data read out by the cycle of read accesses to the banks b1 through b4. If a packet is disassembled on the basis of the amount of data written or read out by the cycle of access to banks, then one segment=(access unit)×(number of banks).
FIG. 18 is a view showing the structure of a packet. It is assumed that a DRAM has 4 banks. Packet data p1a consists of segments s1a and s2a. The segment s1a consists of data d1 through d4. The segment s2a consists of data d5 through d8. If each piece of data is equal to an access unit, then each of the segments s1a and s2a satisfies (one segment=access unit×number of banks).
Packet data p2a consists of segments s11a and s12a. The segment s11a consists of data d1 through d4. The segment s12a consists of only data d5. With the packet data p2a, only the segment s11a satisfies (one segment=access unit×number of banks).
With the conventional DRAM access control shown in FIG. 16 or 17, the rate of transfer to a DRAM does not decrease if a packet which, like the packet data p1a, consists of only segments each of which satisfies (one segment=access unit×number of banks) is handled.
However, if a packet which, like the packet data p2a, includes a segment (segment s11a) that satisfies (one segment=access unit×number of banks) and a segment (segment s12a) that does not satisfy (one segment=access unit×number of banks) is handled, the rate of transfer to a DRAM decreases.
FIG. 19 is a view for describing the reason for a decrease in transfer rate.
[C1, C3, C5, and C7] To write the segment s11a, the data d1, d2, d3, and d4 is written to the banks b1, b2, b3, and b4 by write commands w1, w2, w3, and w4 respectively. When each writing process is begun, a bank constraint is imposed.
[C9] To write the segment s12a, the data d5 is written to the bank b1 by a write command w5.
[C11, C13, and C15] Write access is performed by the segment, so write commands for gaining write access to the banks b2 through b4 are also generated in cycles C11, C13, and C15 respectively. Actually, however, data to be written does not exist, so these cycles are idle cycles.
If a packet in which packet data cannot be divided by (access unit×number of banks) without a remainder is written/read out in this way by the segment, then an idle cycle (useless empty access) occurs and a transfer rate decreases.
It is assumed that a clock rate of an interface used for accessing one DRAM is S and that the rates of writing and reading by a data bus are N (N is proportional to S). If the packet data p2a shown in FIG. 18 is written or read out continuously, then a transfer rate decreases to N×⅝. That is to say, a transfer rate can be increased only to N×⅝ (as can be seen from FIG. 19, the number of pieces of data included in the packet data p2a is 8 and the number of pieces of data which can continuously be written or read out without the occurrence of an idle cycle is 5). If the packet data p2a is the worst case from the viewpoint of performance and N is an effective data rate guaranteed for the device, then the clock rate must be increased to S× 8/5.
For example, it is assumed that an effective data rate to be guaranteed for a memory interface is 10 Gbps (data rates to be guaranteed for writing and reading are 10 Gbps), that 5 data buses are used for one DRAM, and that a clock rate of one data bus is 200 Mbps (=S).
In this case, access to one DRAM can be gained at the data rate of 1 Gbps (=200 Mbps×5). If a calculation is performed simply, then 10 DRAMs are required. Actually, however, writing to and reading from one DRAM cannot be performed at the same time. Accordingly, write access and read access to one DRAM are gained at the data rate of 500 Mbps (500 Mbps=N). In this case, 20 DRAMs are required in order to guarantee a writing data rate of 10 Gbps and a reading data rate of 10 Gbps (10 Gbps (guaranteed writing data rate)=500 Mbps×20 and 10 Gbps (guaranteed reading data rate)=500 Mbps×20).
If the packet data p2a shown in FIG. 18 is written or read out continuously in such a state of the memory interface, actual access is gained in the 5 cycles of the 8 cycles. A writing/reading data rate to be guaranteed is 500 Mbps, but in reality a writing/reading data rate is at most 500×⅝ Mbps.
Access is substantially gained at the low clock rate of 200×⅝ Mbps from the viewpoint of a clock rate of a data bus. Accordingly, to realize the target data rate of 10 Gbps with the idle cycles taken into consideration, the clock rate must be increased to 200× 8/5 (=320 Mbps) (above numeric values are not realistic and are merely set for the sake of simplicity).
With the conventional DRAM access control described in FIG. 17, on the other hand, one segment=(access unit)×(number of DRAMs). If the packet data p2a shown in FIG. 18 is written or read out, the number of DRAMs increases.
It is assumed that an effective data rate guaranteed for a device is R and that the rates of writing to and reading from a DRAM by the use of a data bus are Q (Q is proportional to R). If the packet data p2a is written or read out continuously, then a transfer rate decreases to Q×⅝. Therefore, the number of DRAMs must be increased to R/(Q×⅝).
For example, it is assumed that an effective data rate to be guaranteed for a memory interface is 10 Gbps (data rates to be guaranteed for writing and reading out are 10 Gbps (=R)), that 5 data buses are used for one DRAM, and that a clock rate of one data bus is 200 Mbps.
In this case, write access and read access to one DRAM are gained at the data rate of 500 Mbps (500 Mbps=Q). Accordingly, 20 (=10 Gbps/500 Mbps) DRAMs are required in order to guarantee a writing data rate of 10 Gbps and a reading data rate of 10 Gbps.
If the packet data p2a is written or read out continuously in such a state of the memory interface, actual access is gained only in the 5 cycles of the 8 cycles. A writing/reading data rate to be guaranteed is 500 Mbps, but in reality a writing/reading data rate is at most 500×⅝ Mbps.
Therefore, to realize a target data rate of 10 Gbps, the number of DRAMs must be increased to 32 (=10 Gbps/(500×(⅝) Mbps) (above numeric values are not realistic and are merely set for the sake of simplicity).
As has been described in the foregoing, with the conventional DRAM access control a clock rate or the number of DRAMs must be determined with the occurrence of useless empty access taken into consideration in order to guarantee an effective data rate (descriptions of a write/read switching constraint are omitted in the foregoing, but a clock rate or the number of DRAMs is determined with idle cycles caused by a write/read switching constraint taken into consideration in the case of actually designing a memory interface).
However, there is a limit to a clock rate, so a clock rate required to guarantee an effective data rate cannot always be set. In addition, an increase in the number of DRAMs raises the costs and has an influence on the realization of the entire device. For example, the number of inputs-outputs of the device is limited, the area of a package for mounting shrinks, or wiring over a package becomes difficult. As a result, it is impossible to properly improve the speed of a memory interface.